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control logic/drivers 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view v dd c 0 y 1 y 0 c 1 v dd gnd c out y 2 y out c 2 smo v ss scl r out sda 920 g out sel dual-in-line and soic 10 19 b out r 1 11 12 18 17 fb out fb 2 b 1 13 16 r 2 fb 1 14 15 g 2 b 2 g 1 DG894 vishay siliconix document number: 70072 s-52433erev. d, 06-sep-99 www.siliconix.com faxback 408-970-5600 5-1 component video selector

wide bandwidth: 200 mhz very low crosstalk: 70 db at 5 mhz cmos compatible i 2 c bus compatible fast switchinget on : <200 ns low r ds(on) : 44 single supply capability low insertion loss improved system performance reduced power consumption easily interfaced future system expansion via i 2 c bus component video switching: rgb + sync, s-vhs, y-c, etc. audio/video routing digital tv ate i 2 c bus audio/video systems scart video switching

the DG894 is a monolithic video selector designed for switching a variety of component video signals. the low on-resistance and low capacitance of the DG894 make it ideal for video/audio signal routing. switch control can be through direct cmos addressing or through the two-wire i 2 c bus. the DG894 is built on the vishay siliconix proprietary d/cmos process that combines n-channel dmos switching fets with low-power cmos control logic and drivers. low-capacitance dmos fets are used to achieve high levels of off isolation at low cost.

smo sel sda scl function/switch on 0 0 i 2 c bus operation, address a 0 = a1o 0 1 i 2 c bus operation, address a 0 = a0o 1 0 0 0 all switches off 1 0 0 1 y 0 , c 0 1 0 1 0 y 1 , c 1 1 0 1 1 y 2 , c 2 1 1 0 0 r 1 , g 1 , b 1 , f 1 1 1 0 1 r 2 , g 2 , b 2 , f 2 1 1 1 0 r 1 , g 1 , b 1 , f 1 , y 1 , c 1 1 1 1 1 r 2 , g 2 , b 2 , f 2 , y 2 , c 2

temp range package part number 40 to 85 c 28-pin plastic dip DG894dj 40 to 85 c 28-pin wide body soic DG894dw
DG894 vishay siliconix www.siliconix.com faxback 408-970-5600 5-2 document number: 70072 s-52433erev. d, 06-sep-99

v+ to gnd 0.3 v to 19 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to v 0.3 v to 19 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v to gnd 10 v to 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs gnd 0.3 v to (v+) +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first signal inputs v ss 0.3 v to 8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first continuous current (any terminal) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current (any terminal) pulsed 1 ms, 10% duty cycle max 40 ma . . . . . . . . storage temperature 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package) a 28-pin plastic dip 625 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin wide body soic 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. all leads welded or soldered to pc board. test conditions unless otherwise specified limits 40 to 85 c parameter symbol v dd = 12 v, v ss = 5 v v inh = 3 v, v inl = 1.5 v e temp a min c typ b max c unit analog switch analog signal range d v analog v dd = 12 v, v ss = gnd full 0 4 v analog signal range d v analog v dd = 12 v, v ss = 5 v full 2 2 v drain-source on-resistance r ds(on) i s = 10 ma, v d = 0 v room full 44 51 100 150 resistance match between channels r ds(on) i s = 10 ma , v d = 0 v room 10 source off leakage current i s(off) v s = 4 v, v d = 0 v room full 10 100 0.05 10 100 drain off leakage current i d(off) v d = 4 v, v s = 0 v room full 10 100 0.05 10 100 na total switch on leakage current i d(on) v d = v s = 4 v room full 10 100 0.07 10 100 input input voltage high v inh full 3 2.55 input voltage low v inl full 2.55 1.5 v input threshold v th room 2.55 temp coefficient of input threshold tc th full 200 v/ c input current i in v in = gnd or v dd room full 1 20 0.05 1 20 a output voltage low v ol pin 21, during acknowledge, i ol = 3 ma room 0.4 v dynamic input capacitance d c in pin 21, 22 room 3 10 f on state input capacitance d c s(on) v s = v d = 0 v room 10 15 pf off state input capacitance d c s(off) v s = 0 v room 4 8 pf off state output capacitance d c d(off) v d = 0 v room 4 8 bandwidth d bw r l = 50 , see figure 1 room 200 500 mhz turn on time t on r l = 1 k , c l = 35 pf, 50% to 90% v ss = 5 v , 0 v, v s = 3 v , room 200 ns turn off time t off v ss = 5 v , 0 v , v s = 3 v , see figure 1 room 180 ns scl max clock frequency f scl(max) full 100 khz component crosstalk x talk(co) r in = 10 , r l = 1 k f5mhs fi 2 d3 room 85 db channel crosstalk x talk(ch) in , l f = 5 mhz, see figure 2 and 3 room 85 db
DG894 vishay siliconix document number: 70072 s-52433erev. d, 06-sep-99 www.siliconix.com faxback 408-970-5600 5-3
test conditions unless otherwise specified limits 40 to 85 c parameter symbol v dd = 12 v, v ss = 5 v v inh = 3 v, v inl = 1.5 v e temp a min c typ b max c unit supply voltage positive supply current i+ all control inputs 0 v, 5 v room full 3 4 8 10 ma negative supply current i all control inputs 0 v , 5 v room full 8 10 2.5 3.0 ma notes: a. room = 25 c, full = as determined by the operating temperature suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. guaranteed by design, not subject to production test. e. v in = input voltage to perform proper function. purchase of vishay siliconix DG894 components conveys a license to use them in the i 2 c system as defined by philips. r ds(on) vs. drain voltage t on vs. bipolar supply voltage r ds(on) vs. drain voltage t off vs. bipolar supply voltage r ds(on) drain-source on-resistance ( t on (ns) t off (ns) v+ positive supply (v) v+ positive supply (v) v d drain voltage (v) v d drain voltage (v) 200 180 20 160 140 120 100 80 60 200 180 20 160 140 120 100 80 60 40 v+ = 12 v v = 0 v i s = 10 ma 25 c 85 c 40 c 106 100 94 76 10.8 11.2 13.2 88 82 11.6 12.0 12.4 12.8 85 c 25 c 40 c v = 5 v see figure 1 45.5 43.5 41.5 35.5 10.8 11.2 13.2 39.5 37.5 11.6 12.0 12.4 12.8 85 c 25 c 40 c v = 5 v see figure 1 v+ = 12 v v = 5 v i s = 10 ma 40 25 c 85 c 40 c 4 2 0 2 4 8 60248 6 r ds(on) drain-source on-resistance ( ) )
DG894 vishay siliconix www.siliconix.com faxback 408-970-5600 5-4 document number: 70072 s-52433erev. d, 06-sep-99
component crosstalk channel crosstalk sda output current vs. supply voltage sda output current vs. temperature t on vs. unipolar supply voltage t off vs. unipolar supply voltage t on (ns) t off (ns) current (ma) db current (ma) db f frequency (mhz) f frequency (mhz) v supply (v) temperature (_c) v+ positive supply (v) v+ positive supply (v) 108 100 92 68 10.8 11.2 13.2 84 76 11.6 12.0 12.4 12.8 85 c 25 c 40 c v = 0 v see figure 1 57 54 51 42 10.8 11.2 13.2 48 45 11.6 12.0 12.4 12.8 85 c 25 c 40 c v = 0 v see figure 1 1510 2 4 3 12 10 8 0 40 20 80 6 4 0204060 specification minimum limit 2 100 v+= 12 v v ol = 0.4 v v = 5 v v = 0 v 1510 120 80 40 2 50 60 70 90 100 110 4 3 v ds = +12 v v ss = 5 v r in = 10 r l = 1 k see figure 2 120 80 40 50 60 70 90 100 110 v dd = +12 v v ss = 5 v r in = 10 r l = 1 k see figure 3 10 8 6 0 10.8 11.2 13.2 4 2 11.6 12.0 12.4 12.8 v = 5 v v = 0 v v ol = 0.4 v t a = 25 c specification minimum limit
DG894 vishay siliconix document number: 70072 s-52433erev. d, 06-sep-99 www.siliconix.com faxback 408-970-5600 5-5 figure 1. switching time switch input logic input switch output v s 5 v 0 v 50% 90% t on t off v s r l r l + r ds(on) v o = v s c l (includes fixture and stray capacitance) v v+ in s c l 35 pf d 3 v r l 1 k v o 5 v gnd +12 v figure 2. component crosstalk figure 3. channel crosstalk r l 1 k e.g., y or c e.g., y 1 or c 1 e.g., y 2 or c 2 x talk(co) 20 log 10 v out v in y out or c out 10 1 k b 2 r 2 g 2 x talk(ch) 20 log 10 v out v in b out 10 10 r l 1 k 1 k fb out figure 4. bandwidth fb 1 b 1 +12 v 5 v gnd v+ v c s r l 50 d r g = 75 v s v o
DG894 vishay siliconix www.siliconix.com faxback 408-970-5600 5-6 document number: 70072 s-52433erev. d, 06-sep-99

5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 2 4 6 8 10 12 14 16 18 20 v+ positive supply voltage (v) v negative supply voltage (v) f a data sheet test conditions operating voltage area figure 5.
symbol description y 0 , y 1 , y 2 an analog channel input, typically luminance. c 0 , c 1 , c 2 an analog channel input, typically chrominance. r 1 , r 2 , g 1 , g 2 , b 1 , b 2 , fb 1 , fb 2 an analog channel input, typically aredo, agreeno, ablueo or afast blankingo, as appropriate. gnd analog and digital ground. v dd positive supply voltage a v ss negative supply voltage y out , c out an analog channel output, typically luminance or chrominance, as appropriate r out , g out , b out , fb out an analog channel output, typically aredo, agreeno, ablueo or afast blankingo, as appropriate. smo a low selects serial mode (i 2 c) operation. a high selects cmos operation. sda serial data line b scl serial clock line b sel cmos control line or i 2 c address c select line notes: a. both v dd pins (pin 1 and pin 26) must be connected for proper operation. b. sda and scl pins become cmos control inputs when smo = high. c. the sel pin, in i 2 c bus operation (i.e., with smo low), is the least significant bit of the device address. this allows two devices to operate on the same i 2 c bus, yet retain independent control.
DG894 vishay siliconix document number: 70072 s-52433erev. d, 06-sep-99 www.siliconix.com faxback 408-970-5600 5-7 figure 6. 75 fb 1 b 1 y 2 g 1 r 1 c 1 y 1 c 2 r out g out b out fb out r out g out b out sync out r 2 g 2 b 2 fb 2 smo sel sda +5 v clc114 v ss v dd 5 v +12 v scl gnd c out y out 5 v +5 v channel select control logic left right left 1 right 1 r 1 g 1 b 1 sync 1 left 2 right 2 r 2 g 2 b 2 sync 2 75 75 75 75 75 75 75 75
DG894 vishay siliconix www.siliconix.com faxback 408-970-5600 5-8 document number: 70072 s-52433erev. d, 06-sep-99 i 2 c bus operationergb switching figure 6 shows an inexpensive rgb + stereo selector. the two audio channels are switched via the c, y terminals. the clc114 quad video buffer drives four 75- output lines. characteristics of the i c bus the i c bus interface is ideally suited for communication between different ics or modules. its salient features are: two wire bidirectional serial bus serial data (sda) and serial clock (scl) lines multi-master system (built-in arbitration for multi-master systems) devices have independent clocks master and slave devices can be receivers and/or transmitters. each device has a unique address. maximum bus clock rate of 100 khz. any number of interfaces may be connected to the bus limited only by total capacitance of 400 pf each pin on bus limited to 10-pf capacitance input levels: v il max = 1.5 v (fixed supply operation) v ih min = 3 v (fixed supply operation) v il max = 0.3 v dd (wide range supply operation) v ih min = 0.7 v dd (wide range supply operation) system configuration r p value depends on: number of devices on bus total bus capacitance supply voltage (figure 7). data transfer on the i c bus if the bus is not being used, both sda and scl lines must be left high. every byte put onto the sda line should be eight bits long (msb first), followed by an acknowledge bit, which is generated by the receiving device. each data transfer is initiated with a start condition and ended with a stop condition. the first byte after a start condition is always the address byte. if this is the device's own address, the device will generate an acknowledge by pulling the sda line low during the ninth clock pulse, then accept the data in subsequent bytes until another start or stop condition is detected. the eight bit of the address byte is the read/write bit (high = read from addressed device, low = write to the addressed device) so, for the DG894, the address is only considered valid if the r/w bit is low. data bytes are always acknowledged during the ninth clock pulse by the addressed device. note that during the acknowledge period the transmitting device must leave the sda line high. premature termination of the data transfer is allowed by generating a stop condition at any time. when this happens, the DG894 will remain in the state defined by the last complete data byte transmitted. r p r p master transmitter/ receiver master transmitter peripheral device peripheral device scl sda figure 7.
DG894 vishay siliconix document number: 70072 s-52433erev. d, 06-sep-99 www.siliconix.com faxback 408-970-5600 5-9 sda scl sta sto sda scl start condition stop condition figure 8. start and stop conditions 1 2 7 8 9 1 2 3-8 9 sta start condition sto stop condition ack ack msb sda scl acknowledgement signal from receiver acknowledgement signal from receiver figure 9. data transfer on the i 2 c bus clock line held low while interrupts are serviced byte complete, interrupt within receiver timing specifications of the i c bus i c bus load conditions for timing specifications are as follows: 4 k pull-up resistors to +5 v; 200 pf capacitor to ground. all values are referred to v ih = 3 v, v il = 1.5 v. parameter symbol min max unit scl clock frequency f scl 100 khz bus free before start t buf 4.7 start condition set-up time t su;sta 4.7 start condition hold time t hd;sta 4 scl and sda low period t low 4.7 scl and sda high period t high 4 s scl and sda rise time t r 1.0 scl and sda fall time t f 0.3 data set-up time (write) t su;dat 0.25 data hold time (write) t hd;dat 0* *a transmitter must internally provide at lease a hold time to bridge the undefined region (max 300 ns) of the falling edge of the scl. i c bus protocol the DG894 is a slave receiver type of i c interface and has four allocated addresses, two of which are user programmable through the sel pin. additional addresses may be obtained by a metal mask option for users requiring more than two DG894s on the same i c bus. contact vishay siliconix marketing for further information. after the correct address has been sent, only one data byte is needed to define the switch configuration. subsequent data put onto the bus will update the switches until a stop condition (or another start condition) signals that the device is no longer being addressed. the switches will then remain in their last configuration as long as power is maintained to the chip. power on reset a power on reset function is provided on the DG894 to turn all switches off following power up if the i c mode is selected. in the cmos control mode, the switches are selected according to the state of the control inputs.
DG894 vishay siliconix www.siliconix.com faxback 408-970-5600 5-10 document number: 70072 s-52433erev. d, 06-sep-99 sto t buf t hd;sta t low t high t hd;dat t su;dat t su;sto t r t f t hd;sta sda scl sta sta sto t su;sta figure 10. i 2 c bus timing diagram minimum bit stream to set up DG894 switches sta 1 1 0 1 1 a 1 a 0 r/w ack x x x d 4 d 3 d 2 d 1 d 0 ack sto sta = start condition a 1 = 0 (programmable to a1o with metal mask change) a 0 = sel . address bit set by use (address is inverse of sel logic level) r/w = read/write bit (must be a0o, only write mode allowed for DG894) ack = acknowledge bit (a0o) generated by DG894 d 4 = 0 r 2 , g 2 , b 2, and fb 2 switches off d 4 = 1 r 2 , g 2 , b 2, and fb 2 switches on d 3 = 0 r 1 , g 1 , b 1, and fb 1 switches off d 3 = 1 r 1 , g 1 , b 1, and fb 1 switches on d 2 = 0 y 2 , c 2 , switches off d 2 = 1 y 2 , c 2 , switches on d 1 = 0 y 1 , c 1 , switches off d 1 = 1 y 1 , c 1 , switches on d 0 = 0 y 0 and c 0 switches off d 0 = 1 y 0 and c 0 switches on sto = stop condition data byte address byte

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